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(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 1/14 sram 128 k x 16 sram high speed cmos sram features ordering information ? fast access times : 10, 12, and 15ns ? fast oe access times : 5, 6, and 7ns ? single +3.3v 0.3v power supply ? fully static -- no clock or timing strobes necessary ? all inputs and outputs are ttl-compatible ? three state outputs ? center power and ground pins for greater noise immunity ? easy memory expansive with ce and oe options ? automatic ce power down ? +ljkshuirupdqfh orzsrzhu frqvxpswlrq &026 wulsohsro\ grxeohphwdo surfhvv 44-pin 400mil soj 44-pin 400mil tsop (typeii) product no. acess time (ns) packing type m21l216128a-10j soj m21l216128a-10t 10 tsop m21l216128a-12j soj m21l216128a-12t 12 tsop M21L216128A-15J soj m21l216128a-15t 15 tsop general description the m21l216128a is a high speed, low power asynchronous sram containing 2,097,152 bits and organized as 131,072 by 16 bits, it is produced by high performance cmos process. this device offers center power and ground pins for improved performance and noise immunity. static design eliminates the need for external clocks or timing strobes. for increased system flexibility and eliminating bus contention problems, this device offers chip enable ( ce ), separate byte enable controls ( lb and he ) and output enable ( oe ) with this organization. pin assignment soj top view tsop (typeii) top view 1 2 3 4 5 6 7 8 9 a4 a3 a2 a1 a0 ce dq1 dq2 dq3 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 a5 a6 a7 oe hb lb dq16 dq15 dq14 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 dq4 vcc gnd dq5 dq6 dq7 dq8 we a16 a15 a14 a13 a12 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 dq13 gnd vcc dq12 dq11 dq10 dq9 nc a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 1 0 1 1 a4 a3 a2 a1 a0 ce dq1 dq2 dq3 dq4 vcc gnd dq5 dq6 dq7 dq8 we a16 a15 a14 a13 a12 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 a5 a6 a7 oe hb lb dq16 dq15 dq14 dq13 gnd vcc dq12 dq11 dq10 dq9 nc a8 a9 a10 a11 nc 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 2/14 block diagram ??a?? 512 x 4096 memory array ?a? aa ?? ??? ???? ?a??a? ???? ?? ?? ?? ?? ?? ? ?? ?? ??? ???? dq9 ?? ?? a? ?? pin descriptions pin no. symbol description 1 - 5, 18 - 22, 24-27, 42 - 44 a0 - a16 address inputs 6 ce chip enable input 7 - 10, 13 - 16, 29 - 32, 35 - 38 dq1 - dq16 data inputs/outputs 17 we write enable input 39 lb lower byte enable input (dq1 to dq8) 40 hb higher byte enable input (dq9 to dq16) 41 oe output enable input 11, 33 vcc power 12, 34 gnd ground 23, 28 nc no connection
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 3/14 absolute maximum ratings * voltage on v cc supply relative to vss -0.5v to +4.6v v in ...-0.5v to v cc +1.0v operating temperature, topr .. 0 c to +70 c storage temperature (plastic) .-55 c to +125 c junction temperature +125 c power dissipation ...1.0w short circuit output current 50ma *stresses greater than those listed under absolute maximum. ratings may permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and recommended operations (all temperature ranges ; v cc = 3.3v 0.3v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.2 v cc +0.5 v 1,2 input low (logic 0) voltage v ii -0.5 0.8 v 1,2 input leakage current 0v v in v cc i li -10 10 m a output leakage current output(s) disable 0v v out v cc i lo -5 5 m a output high voltage i oh = -4.0 ma v oh 2.4 v 1 output low voltage i ol = 8.0 ma v ol 0.4 v 1 supply voltage v cc 3.0 3.6 v 1 max description conditions symbol -10 -12 -15 units notes power supply current : operating device selected; ce v il ; v cc =max; f=f max ; outputs open i cc 190 160 130 ma 3 ttl standby ce 3 v ih ; v cc =max; f=f max i sb1 35 30 25 ma cmos standby 1 ce 3 v cc -0.2; v cc = max; all other inputs gnd +0.2 or 3 v cc - 0.2; all inputs static ; f=0 i sb2 10 10 10 ma capacitance description conditions symbol max units notes input capacitance c i 6pf4 input/output capacitance(dq) t a = c 25 ; f=1 mhz v cc =3.3v c i/o 8pf4
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 4/14 ac electrical characteristics (note 5)(all temperature ranges; v cc =3.3v 0.3v) -10 -12 -15 notes description symbol min max min max min max unit read cycle read cycle time t rc 10 12 15 ns access access time t aa 10 12 15 ns chip enable access time t ace 10 12 15 ns output hold from address change t oh 344ns chip enable to output in low-z t clz 3 4 4 ns 4,7 chip disable to output in high-z t chz 567ns4,6,7 output enable access time t oe 567ns output enable to output in low-z t olz 000ns output disable to output in high-z t ohz 567ns4,6 byte enable access time t be 678ns byte enable to output in low-z t blz 0 0 0 ns 4,7 byte disable to output in high-z t bhz 567ns4,6,7 write cycle write cycle time t wc 10 12 15 ns chip enable to end of write t cw 889ns address valid to end of write, with oe high t aw 889ns address setup time t as 000ns address hold from end of write t wr 000ns write pulse width t wp2 10 10 11 ns write pulse width, with oe high t wp1 889ns data setup time t dw 567ns data hold time t dh 000ns write disable to output in low-z t ow 3 4 5 ns 4,7 byte enable to output in high-z t whz 567ns4,6,7 byte enable to end of write t bw 889ns
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 5/14 truth table mode ce we oe le he dq1-dq8 dq9-dq16 power low byte read (dq1-dq8) l h l l h q high-z active high byte read (dq9-dq16) l h l h l high-z q active word read (dq1-dq16) l h l l l q q active low byte write (dq1-dq8) l l x l h d high-z active high byte write (dq9-dq16) l l x h l high-z d active word write (dq1-dq16) l l x l l d d active l x x h h high-z high-z active output disable l h h x x high-z high-z active standby h x x x x high-z high-z stanby ac test conditions input plus levels 0v to 3.0v input rise and fail times 1.5ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 dq 351 dq 5pf z0 =50 30pf 50 3.3v 317 vt=1.5v fig.1 output load equivalent fig.2 output load equivalent
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 6/14 notes 1. all voltages referenced to gnd (vss). 2. overshoot : v ih +6.0v for t t rc /2. undershoot : v il -2.0v for t t rc /2. 3. i cc is given without output current. icc increases with greater output loading and faster cycle times. 4. this parameter is sampled. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. output loading is specified with cl=5pf as in fig.2. transition is measured 500mv from steady static voltage. 7. at any give temperature and voltage conditions, t chz is less than t clz and t whz is less than t ow 8. we is high for read cycle. 9. device is continuously selected. chip enable and output enables are held in their active state. 10. address valid prior to, or coincident with, latest occurring chip enable. 11. t rc =read cycle time. 12. chip enable and write enable can initiate and terminate a write cycle. 13. capacitance derating applies to capacitance different from the load capacitance shown in fig. 1.
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 7/14 timing waveforms read cycle 1 (8, 9) read cycle 2 (7, 8, 9, 10) address t rc t ch t aa dout : don't care : undefined address t rc t aa t clz t blz t olz ce oe dout t chz t ohz hb,lb t ace t be t oe t bhz
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 8/14 timing waveforms (continued) write cycle 1 (7, 12, 13) (write enable controlled with output enable oe active low) d o n ' t c a r e u n d e f i n e d a d d r e s s t w c t w r t b w c e h b , l b w e d i n t c w t d h d o u t t a s t w h z t w p 2 t d w t o w t a w
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 9/14 timing waveforms (continued) write cycle 2 (12, 13) (write enable controlled with output enable oe active high) d o n ' t c a r e u n d e f i n e d a d d r e s s t w c t w r t b w c e h b , l b w e d i n t c w t d h d o u t t a s t w p 1 t d w t a w h i g h - z
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 10/14 timing waveforms (continued) write cycle 3 (12, 13) (chip enable controlled) d o n ' t c a r e u n d e f i n e d a d d r e s s t w c t w r t b w c e h b , l b w e d i n t c w t d h d o u t t w p 1 t d w t a w h i g h - z t a s
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 11/14 timing waveforms (continued) write cycle 4 (12, 13) (byte enable controlled) d o n ' t c a r e u n d e f i n e d a d d r e s s t w c t b w t w r t a s c e h b , l b w e d i n t c w t d h d o u t t w p 1 t d w t a w h i g h - z
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 12/14 packing dimensions 44-lead soj sram(400mil) dimension ( inch ) dimension ( mm ) symbol min nom max min nom max a 0.128 0.138 0.148 3.25 3.51 3.76 a1 0.082 - - 2.08 - - a2 0.025 - - 0.60 - - b 0.015 - 0.020 0.38 - 0.51 b1 0.015 - 0.018 0.38 - 0.46 c 0.007 - 0.013 0.18 - 0.21 c1 0.007 0.008 0.011 0.18 0.20 0.28 d 1.120 1.125 1.130 28.45 28.58 28.70 e 0.435 0.440 0.445 11.05 11.18 11.30 e1 0.394 0.400 0.405 10.01 10.16 10.29 e 0o 10o 0o 10o e 0.050bsc 1.27 bsc
(607 m21l216128a elite semiconduture memory technology inc publication date : sep. 2000 revision : 1.0 13/14 packing dimensions 44-lead tsop(ii) sram(400mil) symbol dimension in mm dimension in inch min norm max min norm max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.042 b0.30 0.45 0.012 0.018 b1 0.30 0.35 0.40 0.012 0.014 0.016 c0.12 0.21 0.005 0.008 c1 0.10 0.16 0.004 0.006 d 18.28 18.41 18.54 0.720 0.725 0.730 zd 0.805 ref 0.0317 ref e 11.56 11.76 11.96 0.455 0.463 0.471 e1 10.03 10.16 10.29 0.395 0.400 0.4 l 0.40 0.59 0.69 0.016 0.023 0.027 l1 0.80 ref 0.031 ref e 0.80 bsc 0.0315 bsc q
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